1. Field of the Invention
The present invention relates to an A/D converter which can be applied to a solid-state imaging device typified by a CMOS image sensor, a solid-state imaging device and a camera system.
2. Description of the Related Art
As for the CMOS image sensor, the same manufacturing process as common CMOS-type integrated circuits can be used for the manufacture thereof as well as driving can be performed by a single power source, and further, an analog circuit and a logic circuit using the CMOS process can be mixed on the same chip.
Accordingly, the CMOS image sensor has plural big advantages such that the number of peripheral ICs can be reduced.
The mainstream of a CCD output circuit is 1-ch output using a FD amplifier having a floating diffusion layer (FD).
On the other hand, the CMOS image sensor has FD amplifiers at respective pixels, the mainstream of the output is a column-parallel output type in which a given one row in a pixel array is selected and these pixels are simultaneously read in the column direction.
This is because it is difficult to obtain sufficient drive performance by the FD amplifiers arranged in the pixels and thus it is necessary to reduce the data rate, therefore, parallel processing is advantageous.
An awful lot of readout (output) circuits of pixel signals in the column-parallel output CMOS image sensor have been proposed.
One of the most advanced forms of these circuits is a type having an analog-digital converter (hereinafter, abbreviated as ADC) in each column, in which pixel signals are taken out as digital signals.
The CMOS image sensor on which the column-parallel type ADCs are mounted is disclosed in, for example, JP-A-2005-278135 (Patent Document 1) and W. Yang et. al., “An Integrated 800×600 CMOS Image System” ISSCC Digest of Technical Papers, pp. 304-305, February 1999) (Non-patent document 1).
FIG. 1 is a block diagram showing a configuration example of a column-parallel ADC mounted solid-state imaging device (CMOS image sensor).
A solid-state imaging device 1 includes a pixel section 2, a vertical scanning circuit 3, a horizontal transfer scanning circuit 4 and a column processing circuit group 5 having an ADC group as shown in FIG. 1.
The solid-state imaging device 1 further includes a digital-analog converter (hereinafter, abbreviated as DAC) 6 and amplifier circuits (S/A) 7.
The pixel section 2 is configured by unit pixels 21 each having a photodiode (photoelectric conversion element) and an in-pixel amplifier being arranged in a matrix state.
In the column processing circuit group 5, plural columns of column processing circuits 51 each forming the ADC in each column are arranged.
Each column processing circuit (ADC) 51 includes a comparator 51-1 comparing a reference voltage Vslop which is a ramp waveform (RAMP) obtained by changing a reference voltage generated by the DAC 6 into a step-shape with an analog signal obtained from pixels of each row line through a vertical signal line.
Each column processing circuit 51 further includes a latch (memory) which counts comparison time of the comparator 51-1 and holds the count result.
The column processing circuits 51 have an n-bit digital signal converting function and are arranged with respect to respective vertical signal lines (column line) 8-1 to 8-n, which constitutes a column-parallel ADC block.
Outputs of respective memories 51-2 are connected to horizontal signal lines 9 having, for example, a k-bit width. K-pieces of amplifier circuits 7 corresponding to the horizontal transfer lines 9 are arranged.
FIG. 2 shows a timing chart of the circuit of FIG. 1.
In each column processing circuit (ADC) 51, an analog signal (potential Vs1) read to the vertical signal line 8 is compared with the reference voltage Vslop which changes into a step-shape in the comparator 51-1.
At this time, counting is performed in the latch 51-2 until levels of the analog potential Vs1 and the reference voltage Vslop intersect and an output from the comparator 51-1 is inverted, then, the potential of the vertical signal line (analog signal) Vs1 is converted into a digital signal (A/D converted).
The A/D conversion is made twice in one reading.
In the first conversion, reset levels (P phase) of the unit pixels 21 are read to the vertical signal lines 8 (8-1 to 8-n) and A/D conversion is made.
The reset levels P-phase include variations according to pixels.
In the second conversion, signals (D phase) which have been photoelectrically converted in respective unit pixels 21 are read to the vertical signal lines 8 (8-1 to 8-n) and A/D conversion is made.
The D phase also includes variations according to pixels, therefore, (D phase level-P phase level) is executed to thereby realize correlated double sampling (CDS).
Signals converted into digital signals are recorded in the latches (memories) 51-2, sequentially read to the amplifier circuits 7 through the horizontal transfer lines 9 by the horizontal transfer scanning circuit 4 and finally outputted.
Accordingly, column-parallel output processing is performed.